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Frequency synthesizer for microwave communication systems
Klapil, Filip ; Vondra, Vlastimil (referee) ; Kasal, Miroslav (advisor)
The main aim of the thesis is to develop a solution of a frequency synthesizer for a microwave communication systems. Specifically, it suggests a design for frequency synthesizer with phase-locked loop. At beginning of the thesis the principle and basic properties of this method of signal generation are explained. Then it is followed by a brief discussion of the parameters of synthesizers and their influence on design. Another part of the work is the analysis of circuit the frequency synthesizer with the phase-locked loop MAX2871, which is followed by a proposal for the design of the frequency synthesizer module hardware. The last part of the work deals with practical implementation, verification of function and measurement of achieved parameters and their evaluation.
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Wideband 6GHz RF Signal Generator
Mička, Josef ; Kubíček, Michal (referee) ; Urbanec, Tomáš (advisor)
The goal of this thesis is a design of a wideband high frequency generator with an adjustable output amplitude. The generator is based on a frequency synthesizer ADF4355. The power level of an output signal is adjustable by an attenuator HMC1119. The created generator is accesisible trough an user-friendly control panel or by SCPI commands. Frequency synthesis can run in an integer mode or a fractional mode. The output signal has a very low phase noise when it is running in the integer mode.
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Frequency Synthesizers
Lapčík, Josef ; Špaček, Jiří (referee) ; Dřínovský, Jiří (advisor)
This diploma thesis concerns with analysis and dividing of frequency synthesizers and design of DDS, PLL synthesizers. Base types of frequency synthesizers are described including differences between methods of their operation. Base circuits of both – DDS and PLL synthesizers and other important circuits are described in details at design part of this thesis. Design of DDS and PLL synthesizer is described in particular sections. Both synthesizers are directly realized and stand-alone control applications are created. PLL synthesizer is also ready to control thru Agilent VEE program environment. Particular example application is designed in Agilent VEE. This application is used as basis of attached lab project.
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Frequency-to-Voltage Converter
Šindelář, Michal ; Bejček, Ludvík (referee) ; Beneš, Petr (advisor)
This bachelor’s thesis deals with the issue of the transfer frequency to voltage focusing on dynamics and accuracy. The goal of this thesis is the design and implementation of the converter based on the input arguments. The graph evaluates the tradeoff between dynamics and accuracy. It is possible to choose a more suitable solution to transfer frequency to voltage for the specified requirements.
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Gas flow measurement
Kozák, Matěj ; Uher, Miroslav (referee) ; Beneš, Petr (advisor)
This thesis deals with the problem of designing vortex flow meter for a nominal range of 40 l.min-1. It describes the problems of vortex bodies and choice of methods for detection of vortices. The thesis includes solution of various problems in the design, which were published in scientific articles or patents. The following describes the design solution vortex flow meter for the specified range, which uses ultrasonic sensors to vortices detection. The proposed flow meter is calibrated with reference flow meter and compared with commercially produced vortex flow by the TST electronics and Burkert companies, which are designed for the specified ranges.
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Design and Simulation of Single Phase Active Rectifier
Bareš, Jiří ; Huták, Petr (referee) ; Klíma, Bohumil (advisor)
This thesis deals with single-phase active rectifier, strategy of control and simulation of its model. In the beginning of this work a principle of rectifier is described along with transistor switching system, which has impact on shape of input current. Dimensioning of rectifier for assembling model and designing of control, including phase-locked loop and regulators follows. In the end assembled model and its simulation is described.
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Synchronized sources of clock signals
Florián, Antonín ; Lazar,, Josef (referee) ; Drexler, Petr (advisor)
This thesis deals with design of synchronized sources of time signal. The first part of the thesis deals with the theory the crystal resonators, crystal oscillators and PLL. The second part of the thesis deals with the crystal oscillator with 10MHz frequency. In the oscillator is use of SC cut crystal. The third part of the work deals with method of synchronization. To synchronization is use of PLL.
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Design of the voltage controlled oscillator
Richter, Vladimír ; Pavlík, Michal (referee) ; Háze, Jiří (advisor)
This bachelor thesis deals with the issues of voltage controlled oscillators. It analyses their current state and provides the examples of them. It also describes phase locked loop stages and the usage of voltage controlled oscillators in phase locked loops. The main aim of this thesis is to design a voltage controlled oscillator and use it to realize the important simulations.
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Digital audio interface converter with an external PLL
Klubus, Jan ; Balík, Miroslav (referee) ; Hanák, Pavel (advisor)
The design of the learning hardware for the laboratory role of the BSHE, which will serve as a test sample, and will permit students to display signals in individual parts of the circuit using an oscilloscope. This device convert the S / PDIF and AES3 signal, it have a line and headphone output and the phase lock loop will be output separately for signal tracking.
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